1. Field of the Disclosure
The present disclosure generally relates to test structures and a method of forming an according test structure, and, more particularly, to test structures to measure a source/drain-contact-to-a-back-gate-voltage breakdown.
2. Description of the Related Art
For next generation technologies, semiconductor-on-insulator (SOI) technology is an attractive candidate to push forward the frontiers imposed by Moore's law. Particularly, fully depleted SOI (FDSOI) techniques seem to provide promising technologies that allow the fabrication of semiconductor devices at technology nodes of 28 nm and beyond. Aside from FDSOI techniques allowing the combination of high performance and low power consumption, complemented by excellent responsiveness to power management design techniques, the fabrication processes as employed in FDSOI techniques are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques.
In general, a MOSFET as fabricated by SOI techniques is a semiconductor device (MOSFET) comprising a gate structure (with a gate electrode and a gate oxide) formed on an SOI substrate, where a semiconductor layer, such as silicon, germanium or silicon germanium, is formed on an insulator layer, e.g., a buried oxide (BOX) layer, which, in turn, is formed on a semiconductor substrate material, such as silicon. Conventionally, there are two types of SOI devices: partially depleted SOI (PDSOI) and fully depleted SOI (FDSOI) MOSFETs. For example, in an N-type PDSOI MOSFET, a P-type film being sandwiched between the gate oxide (GOX) and the BOX layer is so large that the depletion region cannot cover the whole P region. Therefore, to some extent, PDSOI devices behave like bulk MOSFETS.
In FDSOI devices, the depletion region covers the whole semiconductor layer. Since, in FDSOI techniques, the semiconductor layer supports fewer depletion charges than the bulk, an increase in inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds for FDSOI devices.
Compliance with Moore's law demands smaller ground rules for implementing ultra large scale integration (ULSI), as well as to further increase the integration density on a single chip, wherein increasingly scaled structures are formed in and above semiconductor substrates, leading to less space being available for device structures per footprint. Therefore, the continuing down-scaling of semiconductor devices to increasingly smaller scales raises various issues.
For example, an issue of FDSOI technologies at ULSI technology nodes, e.g., at 28 nm and beyond, is given by an increasing risk for “CA punch down” caused by misalignment of a source/drain contact (often referred to as “CA”) relative to a source/drain region and a gate structure, respectively, or a pulled-back raised source/drain region. The “CA punch down” indicates a source/drain contact that punches through the source/drain region and at least partially extends into the BOX layer below the source/drain region. As a consequence, a spacing between the contact and an underlying upper surface of the base semiconductor substrate, particularly, in FDSOI techniques employing a back gate biasing, an upper surface of the back gate, may be reduced, resulting in a weak spot for dielectric breakdown and possibly a short between the source/drain contact and the back gate, where a short leads to a failure of the whole chip under fabrication.
An intermediate approach as presently followed in FDSOI introduction is represented as hybrid technology where all digital logic and memory devices exploit the benefits of FDSOI, while a few semiconductor device structures stay on bulk: for example, some analog or specific structures that designers prefer to keep on bulk for any reason (legacy, etc.)—assuming the power/performance/variability crisis faced at the next nodes is not too acute for such device structures.
In view of the above-described situation, it is, therefore, desirable to identify possible semiconductor devices having misaligned source/drain contacts and/or pulled-back raised source/drain regions for reducing the risk of dielectric breakdown and shorts in advanced semiconductor devices.